1. Field of the Invention
A technique disclosed in this specification relates to a semiconductor device.
2. Description of Related Art
Japanese Patent Application Publication No. 2009-117593 (JP 2009-117593 A) discloses a SiC semiconductor device of trench gate type. This semiconductor device is formed with an n-type drift layer on a SiC substrate and a trench that extends from an upper surface of the SiC substrate to the drift layer. On the drift layer, a p-type base region is formed to contact a side surface of the trench. P-type deep layers are formed to interpose the base region therebetween and to separate from the trench. The deep layer is formed in a same depth as the trench or to a position deeper than the trench, and is doped at same concentration as the base region or higher. According to the technique disclosed in JP 2009-117593 A, when a reverse bias voltage is applied to the semiconductor device, a depletion layer that extends from a p-n junction between the p-type deep layer and the n-type drift layer greatly extends to the drift layer side. This can alleviate intensity of an electric field in a gate oxide film formed in the trench and thus can prevent breakage of the gate oxide film.
In recent years, researches and developments of high-voltage semiconductor devices using a SiC have actively been pursued. Compared with Si semiconductor devices, a thickness of the drift layer in the SiC semiconductor devices with the same withstand voltage can be thinned. The SiC increases a withstand voltage of the semiconductor device; however, because the electric field that is applied to the gate oxide film is also strengthened, there is a need for further alleviating the electric field that is applied to the gate oxide film. In order to form an electric field alleviating layer in the further vicinity of the gate oxide film for this purpose, it is considered to form a semiconductor region that contacts a lower face of the base region and is doped at the same concentration as the base region or higher. When such a semiconductor region is formed from the lower surface of the base region to a position in the same depth as the trench or deeper, the electric field applied to the gate oxide film is further alleviated, and thus a withstand voltage property of the semiconductor device can be enhanced (the semiconductor region is hereafter referred to as the “electric field alleviating layer”).
However, in the above-described semiconductor device that includes the electric field alleviating layer, if the excess reverse bias voltage is temporarily applied, the avalanche breakdown may occur at an interface between the electric field alleviating layer and the drift layer. When the avalanche breakdown occurs, an electron-positive hole pair is produced at the interface, and the thus-produced positive hole moves to the base region. In general, the positive hole that has moved to the base region is discharged from a p-type contact region to a source electrode. However, due to low impurity concentration, the base region has high resistance. Accordingly, a transfer rate of the positive hole is low in the base region, and the positive holes are likely to be accumulated in the base region. Therefore, the positive hole that is produced at the avalanche breakdown cannot be discharged from the contact region in a timely manner. As a result, a potential of the base region rises, and a parasitic npn bipolar transistor that is formed of an n-type source region formed above the base region, the p-type base region, and the n-type drift layer is operated to possibly cause a flow of overcurrent between the source region and a drain due to a latchup.